/*
	ARMada
	Decode stage
*/

module decode
(
	input clk,
 	input rst,

	input [31:0] instr_in,
	input [31:0] wb_data,
	input [3:0] wb_reg,

	output [3:0]  xa, //destination

	output [31:0] xb, //sources...
	output [31:0] xc,
	output [31:0] xd,
	output [31:0] imm,

	output [5:0] operand,

	output [31:0] instr_out
);

//GPR R0-R14
reg[31:0] gpr[14:0];  //general purpose registers R14-R00
reg[31:0] status_reg; //status
//Status Registers

endmodule
